• hzr414ak posted an update 1 week, 2 days ago

    Model: MY-SAMA5-CB200-5D36
    Atmel® | SMART SAMA5
    ARM Cortex-A5
    536MHz (850DMIPS)
    256MB DDR3 (64 Bit)
    256MB Nandflash, up to 1G
    Industrial grade
    -40° to 85° C Temp
    Top view)
    Rear view
    SAMA5D3 diagram
    SAMA5D3 block diagram
    SAMA5D3 MPU difference
    SAMA5D36 critical parameter
    Pin Count:324
    Max. Operating Freq. (MHz):536 MHz
    Max I/O Pins:160
    Ext Interrupts:160
    USB Transceiver:3
    USB Speed:Hi-Speed
    USB Interface:Host, Device
    TWI (I2C):3
    SD / eMMC:3
    Graphic LCD:Yes
    Camera Interface:Yes
    ADC Channels:12
    ADC Resolution (bits):12
    ADC Speed (ksps):1000
    Resistive Touch Screen:Yes
    Crypto Engine:AES/DES/SHA/TRNG
    SRAM (Kbytes):128
    External Bus Interface:1
    NAND Interface:Yes
    Temp. Range (deg C):-40 to 105
    I/O Supply Class:1.8/3.3
    Operating Voltage (Vcc):1.08 to 1.32
    Output Compare Channels:6
    Input Capture Channels:6
    PWM Channels:4
    32kHz RTC:Yes
    MPU / MMU:No / Yes
    Quadrature Decoder Channels:0
    Video Decoder:No
    MY-IMX6-CB200 configuration
    hardware configuration
    memory256MBup to 512MB
    storage256MBsupport up to 2GB
    SPI Flash2Msupport programming
    boot modeSPI bootensure the stability and reliability of products
    working temperature range
    Industrial grade: -40°C ~ 85°C
    Industrial expansion grade: -40°C ~ 105°C
    operation system support
    kernel: Linux-3.18
    interface:command line
    model command
    name of model
    MY-SAMA5-CB200-MPU specification-memory capacity-storage capacity
    MPU specification
    D36ACN, D36ACNR:industrial expansion
    D36ACU, D36ACUR: industrial
    memory capacity
    256MB: 256G memory
    storage capacity
    256MB: 256G storage
    example of model
    MY-SAMA5-CB200 definition
    No.PinDefault signalDefault InterfaceMultiplexMultiplexDefault InterfaceDefault signalPinNo.
    15PC0ETX0TIOA3 SSC0RK0PC1916
    17PC2ERX0TCLK3 TF0PC1718
    21PC9EMDIO  RD0PC2122
    25PC29URXD0ISI_D8|PWMFI2 TD0PC1826
    27GND_POWER      GND_POWER28
    33PC25SPI1_NPCS0    GND_POWER34
    37PC24SPI1_SPCK    GND_POWER38
    43PA10LCDDAT10  LCDDAT15PA1544
    47PA12LCDDAT12  LCDDAT1PA148
    63PA7LCDDAT7  LCDDAT11PA1164
    69PD31  PCK1|AD11ISI_D10|SPI1_NPCS2TWI1TWCK1PC2770
    73PD29AD9AD  MCI0MCI0_DA3PD474
    75PD28AD8  MCI0_DA1PD276
    77PD27AD7  MCI0_CDAPD078
    79PD26AD6  MCI0_CKPD980
    81PD23AD3  MCI0_DA2PD382
    83PD22AD2  MCI0_DA0PD184
    85PD24AD4 PWML2|TIOB0MCI0_DA5PD686
    87PD21AD1 PWML3MCI0_DA7PD888
    95PD7PWMH3MCI0_DA6|TCLK0  RXD0PD1796
    101PB7GRX3RK1 SPI0_MOSIPD11102
    109PB18G125CK GTX7MCI1MCI1_DA2PB22110
    123PB6GRX2TD1 RXD1PB28124
    125PB5GRX1PWML1 TXD1PB29126
    127PB16GMDC GRX7CTS1PB26128
    131BMS      DIBN132
    133NRST      DIBP134
    135TDI    DEBUGDTXDPB31136
    137JTAGSEL    DRXDPB30138
    141TMSSWDIO     GND_POWER142
    147WKUP    USBB HHSDPB148
    149SHDN      HHSDMB150
    151D7 EBI:Dx  USBC HHSDMC152
    153D6     HHSDPC154
    155D5  LCDDAT23|TIOB2EBINCS2PE28156
    157D4  LCDDAT22|TIOA2NCS1PE27158
    159D3  USART2:CTS2A23PE23160
    161D2  USART2:RXD2A25PE25162
    163D1  USART2:TXD2NCS0PE26164
    165D0   A20PE20166
    169PE5A5 TCLK2NWR1/NBS1PE29170
    171PE6A6 USART3:RXD3A18PE18172
    173PE13A13 USART3:TXD3A19PE19174
    175PE15A15SCK3PWML1|IRQMMC1:VDD_EN PE31176
    177PE8A8 NWAITMMC1:CD PE30178
    179PE10A10 GPIO:LEDEBI:AxA4PE4180
    181PE14A14 GPIO:LEDA2PE2182
    185PE0A0/NBS0  A7PE7186
    187PE11A11 RTS3A17PE17188
    189GND_POWER    A9PE9190
    191GND_POWER    A12PE12192
    193GND_POWER      VCC_3V3194
    195GND_POWER      VCC_3V3196
    197GND_POWER      VCC_3V3198
    199GND_POWER      VCC_3V3200
    instruction1: in the column of “multiplex signal” signal highlighted in yellow are the ones realized by MY-SAMA5-EK200
    instruction2:pins led out by MY-SAMA5-CB200-D36 are PA0~PA31、PB0~PB31、PC0~PC31、PD0~PD12、PD14~PD31、PE0~PE20、PE23~PE31
    SAMA5D3 MPU introduction
    SAMA5 main features
    high performance
    SAMA5 series is designed an an improvement for ARM Cortex-A5 in terms of insufficient power,its components can provide processing capacity up to 945DMIPS at power consumption less than 150mW*1.58 DMIPS/MHz ARM Cortex-A5 kernel the maximum working frequency(945DMIPS) is upt to 600 MHz 64bit internal bus architecture,32bit DDR controller which can offer band width of up to 1600 MB/s
    Neon and floating point calculation unit is used for highly precise calculation and fast data process capability of ARM Cortex-A5 FPU is 3 times higher than that of ARM Cortex-A8 FPU L2 cache,is used to improve performance of the whole system
    low power consumption
    · SAMA5 components can lower effectively power consumption in all modes by applying innovative technology and fulfill following objectives:
    · with all external devices activated,it can provide up to 536MHz working frequency with less than 150mW(in working mode)
    · in low power consumption mode with SRAM and register kept,the power consumption is as low as 0.5mW and waking up takes only less than backup mode of RTC(real time clock),the power consumption is about 1.2μA
    · the best choice for the systems powered by battery
    SAMA5 components embed various kinds of high class communication external devices,so it is the best choice for network bridge and gateway
    · support IEEE1588 ethernet MAC and Gbps ethernet MAC,dual CAN ports
    · can be configured to 3 hosts or two host+3 high speed USB interfaces of one component port
    · multiple SDIO/SD/MMC interface、UART、SPI、TWI、soft modulator、CMOS image sensor interface、ADC、32 timer and ect. please refer to “component overview” tab for more details.
    enhanced user interface
    · you can create upt to date user interface in fashionable,stable style with SAMA5 MPU.
    · graphic LCD controller features synthesis and superimposition of image and integration( such as αblend,zoom,color transform and rotation)
    · 720p hardware video decoder is used to support playback of vedio in current main stream standard
    · resistance touch screen interface
    · CMOS image sensor interface
    safety of SAMA5 series incudes functions of preventing copy,ensuring facticity and protecting application communication and data storage
    satefy boot
    · hardware encrypt engine,such as high class encrypt standard(AES)/triple data encription standard (DES)、RSA (Rivest-Shamir-Adleman) and ECC(elliptic curve crypto) and secure hash algorithm(SHA) and true Random number generator(TRNG)
    · immediately encrypt code/decode through external DDR memory
    · detect tamper of pin, to protect system from physical intruding
    · cipher key and data safe storage
    · ARM trusted area is for the partition among system,peripherals and internal resources to isolate the main software related to safety with environment operating system
    functions possessed by SAMA5 can meet easily with the safety standard such as IEC61508
    · main crystal oscillator cock can work as a fault detector
    · power on and reset
    · independent watch dog timer
    · writing protection of register
    · memory management unit allow a setting of zone prorection in the memory
    · ICM(monitor of integrity) based on SHA is used to verify integrity of content in memory
    · Arm trusted zone
    low cost of system
    · SAMA5 realize the purpose of maximum flexibility and the the same time reducing demands for other expensive components by high integrity of system
    · 0.8mm ball spacing package simplify PCB design and lower cost
    · scheme for minimum low consumption need Chip discrete power and low cost
    · 3 high speed USB ports help to save the cost for external integrator
    · impedance control on memory circuit of DDR(dual data rate) save external resistors
    · embedded RTC save external components
    · solution with soft modulator integrated save cost for adding external modulator
    SAMA5D3 Features
    · ARM Cortex-A5 Processor with ARM v7-A Thumb2? Instruction Set
    · CPU Frequency up to 536 MHz
    · 32 Kbyte Data Cache, 32 Kbyte Instruction Cache, Virtual Memory System Architecture (VMSA)
    · Fully Integrated MMU and Floating Point Unit (VFPv4)
    · One 160 Kbyte Internal ROM Single-cycle Access at System Speed, Embedded Boot Loader: Boot on 8-bit
    · NAND Flash, SDCard, eMMC, serial DataFlash?, selectable Order
    · One 128 Kbyte Internal SRAM, Single-cycle Access at System Speed
    · High Bandwidth 32-bit Multi-port Dynamic RAM Controller supporting 512 Mbyte 8 bank DDR2/LPDDR/LPDDR2 with datapath scrambling
    · Independent Static Memory Controller with datapath scrambling and SLC/MLC NAND Support with up to 24-bit Error Correcting Code (PMECC)
    System running up to 166 MHz
    · Reset Controller, Shut Down Controller, Periodic Interval Timer, Watchdog Timer and Real-time Clock
    · Boot Mode Select Option, Remap Command
    · Internal Low-power 32 kHz RC Oscillator and Fast 12 MHz RC Oscillator
    · Selectable 32768 Hz Low-power Oscillator and 12 MHz Oscillator
    · One 400 to 1000 MHz PLL for the System and one PLL at 480 MHz optimize d for USB High Speed
    · 39 DMA Channels including two 8-channel 64-bit Central DMA Controllers
    · 64-bit Advanced Interrupt Controller
    · Three Programmable External Clock Signals
    · Programmable Fuse Box with 256 fuse bits, 192 of them available for Customer
    Low Power Management
    · Shut Down Controller
    · Battery Backup Registers
    · Clock Generator and Power Management Controller
    · Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities
    · LCD TFT Controller with Overlay, Alpha-blending,Rotation, Scaling and Color Space Conversion
    · ITU-R BT. 601/656 Image Sensor Interface
    · Three HS/FS/LS USB Ports with On-Chip Transceivers
    · One Device Controller
    · One Host Controller with Integrated Root Hub (3 Downstream Ports)
    · One 10/100/1000 Mbps Gigabit Ethernet MAC Controller (GMAC) with IEEE1588 support
    · One 10/100 Mbps Ethernet MAC Controller (EMAC)
    · Two CAN Controllers with 8 Mailboxes, fully Compliant with CAN 2.0 Part A and 2.0 Part B
    · Softmodem Interface
    · Three High Speed Memory Card Hosts (eMMC 4.3 and SD 2.0)
    · Two Master/Slave Serial Peripheral Interfaces
    · Two Synchronous Serial Controllers
    · Three Two-wire Interface up to 400 Kbit/s supporting I2C Protocol and SMBUS
    · Four USARTs, two UARTs, one DBGU
    · Two Three-channel 32-bit Timer/Counters
    · One 4-channel 16-bit PWM Controller
    · One 12-channel 12-bit Analog-to-Digital Converter with Resistive Touch-Screen function
    · Power-on Reset Cells
    · Independent Watchdog
    · Main Crystal Clock Failure Detection
    · Write Protection Registers
    · SHA: Supports Secure Hash Algorithm (SHA1, SHA224, SHA 256, SHA384, SHA512)
    · Memory Management Unit
    · TRNG: True Random Number Generator
    · Encryption Engine
    · AES: 256-bit, 192-bit, 128-bit Key Algorithm, Compliant with FIPS PUB 197 Specifications
    · TDES: Two-key or Three-key Algorithms, Co mpliant with FIPS PUB 46-3 Specifications
    · Atmel? Secure Boot Solution
    · Five 32-bit Parallel Input/Output Controllers
    · 160 I/Os
    · Input Change Interrupt Capability on Each I/O Line, Selectable Schmitt Trigger Input
    · Individually Programmable Open-drain, Pull-up and Pull-down Resistor, Synchronous Output, Filtering
    · Slew Rate Control on High Speed I/Os
    · Impedance Control on DDR I/Os
    · 324-ball LFBGA, 15 x 15 x 1.4 mm, pitch 0.8 mm
    · 324-ball TFBGA, 12 x 12 x 1.2 mm, pitch 0.5 mm
    SAMA5D3 Embedded Characteristics
    · 12-bit key-protected programmable counter
    · Watchdog Clock is independent from Processor Clock
    · Provides reset or interrupt signals to the system
    · Counter may be stopped while the processor is in debug state or in idle mode
    · Ultra Low Power Consumption
    · Full Asynchronous Design
    · Gregorian Calendar up to 2099
    · Programmable Periodic Interrupt
    · Safety/security features:
    · Valid Time and Date Programmation Check
    · Up to 32 Programmable I/O Lines
    · Fully Programmable through Set/Clear Registers
    · Multiplexing of Four Peripheral Functions per I/O Line
    · For each I/O Line (Whether Assigned to a Peripheral or Used as General Purpose I/O)
    · Input Change Interrupt
    · Programmable Glitch Filter
    · Programmable Debouncing Filter
    · Multi-drive Option Enables Driving in Open Drain
    · Programmable Pull-Up on Each I/O Line
    · Pin Data Status Register, Supplies Visibility of the Level on the Pin at Any Time
    · Additional Interrupt Modes on a Programmable Event: Rising Edge, Falling Edge, Low-Level or High-Level
    · Lock of the Configuration by the Connected Peripheral
    · Synchronous Output, Provides Set and Clear of Several I/O Lines in a Single Write
    · Register Write Protection
    · Programmable Schmitt Trigger Inputs
    · Programmable I/O Drive
    · Dual AHB Master Interface
    · Supports Single Scan Active TFT Display
    · Supports 12-, 16-, 18- and 24-bit Output Mode through the Spatial Dithering Unit
    · Asynchronous Output Mode Supported (at synthesis time)
    · 1, 2, 4, 8 bits per pixel (palletized)
    · 12, 16, 18, 19, 24, 25 and 32 bits per pixel (non palletized)
    · Supports One Base Layer (background)
    · Supports Two Overlay Layer Windows
    · Supports One High End Overlay (HEO) Window
    · Supports One Hardware Cursor, Fixed or Free Size
    · Hardware Cursor Fixed Size on the following patterns: 32×32, 64×64 and 128×128
    · Little Endian Memory Organization
    · Programmable Timing Engine, with Integer Clock Divider
    · Programmable Polarity for Data, Line Synchro and Frame Synchro.
    · Display Size up to 2048×2048, or up to 720p in video format
    · Color Lookup Table with up to 256 entries and Predefined 8-bit Alpha
    · Programmable Negative and Positive Row Striding for all Layers
    · Programmable Negative and Positive Pixel Striding for all Overlay1, Overlay2 and HEO layers
    · High End Overlay supports 4:2:0 Planar Mode and Semiplanar Mode
    · High End Overlay supports 4:2:2 Planar Mode, Semiplanar Mode and Packed
    · High End Overlay includes Chroma Upsampling Unit
    · Horizontal and Vertical Rescaling unit with Edge Interpolation and Independent Non Integer Ratio
    · Hidden Layer Removal supported.
    · Integrates Fully Programmable Color Space Conversion
    · Overlay1, Overlay2 and High End Overlay Integrate Rotation Engine: 90, 180, 270
    · Blender Function Supports Arbitrary 8-bit Alpha Value and Chroma Keying
    · DMA User interface uses Linked List Structure and Add-to-queue Structure
    · ITU-R BT. 601/656 8-bit Mode External Interface Support
    · Supports up to 12-bit Grayscale CMOS Sensors
    · Support for ITU-R BT.656-4 SAV and EAV Synchronization
    · Vertical and Horizontal Resolutions up to 2048*2048
    · Preview Path
    · Up to 2048*2048 in Grayscale Mode
    · Up to 640*480 in RGB Mode
    · 32 Bytes FIFO on Codec Path
    · 32 Bytes FIFO on Preview Path
    · Support for Packed Data Formatting for YCbCr 4:2:2 Formats
    · Preview Scaler to Generate Smaller Size image
    · Programmable Frame Capture Rate
    · VGA, QVGA, CIF, QCIF Formats Supported for LCD Preview
    · Custom Formats with Horizontal and Vertical Preview Size as Multiples of 16 Also Supported for LCD Preview
    · 1 Device High Speed
    · 1 UTMI transceiver shared between Host and Device
    · USB v2.0 High Speed Compliant, 480 Mbit/s
    · 16 Endpoints up to 1024 bytes
    · Embedded Dual-port RAM for Endpoints
    · Suspend/Resume Logic (Command of UTMI)
    · Up to Three Memory Banks for Endpoints (Not for Control Endpoint)
    · 8 KBytes of DPRAM
    · Compliant with Enhanced HCI Rev 1.0 Specification
    · Compliant with USB V2.0 High-speed
    · Supports High-speed 480 Mbps
    · Compliant with OpenHCI Rev 1.0 Specification
    · Compliant with USB V2.0 Full-speed and Low-speed Specification
    · Supports both Low-speed 1.5 Mbps and Full-speed 12 Mbps USB devices
    · Root Hub Integrated with 3 Downstream USB HS Ports
    · Embedded USB Transceivers
    · Supports Power Management
    · Hosts (A and B) High Speed (EHCI), Port A shared with UDPHS
    · Compatible with IEEE Standard 802.3
    · 10, 100 and 1000 Mbps operation
    · Full and half duplex operation at all supported speeds of operation
    · Statistics Counter Registers for RMON/MIB
    · MII/GMII/RGMII interface to the physical layer
    · Integrated physical coding
    · Direct memory access (DMA) interface to external memory
    · Programmable burst length and endianism for DMA
    · Interrupt generation to signal receive and transmit completion, or errors
    · Automatic pad and cyclic redundancy check (CRC) generation on transmitted frames
    · Frame extension and frame bursting at 1000 Mbps in half duplex mode
    · Automatic discard of frames received with errors
    · Receive and transmit IP, TCP and UDP checksum offload. Both IPv4 and IPv6 packet types supported
    · Address checking logic for four specific 48-bit addresses, four type IDs, promiscuous mode, hash matching of
    · unicast and multicast destination addresses and Wake-on-LAN
    · Management Data Input/Output (MDIO) interface for physical layer management
    · Support for jumbo frames up to 10240 bytes
    · Full duplex flow control with recognition of incoming pause frames and hardware generation of transmitted pause
    · frames
    · Half duplex flow control by forcing collisions on incoming frames
    · Support for 802.1Q VLAN tagging with recognition of incoming VLAN and priority tagged frames
    · Support for 802.1Qbb priority-based flow control
    · Programmable Inter Packet Gap (IPG) Stretch
    · Recognition of IEEE 1588 PTP frames
    · IEEE 1588 time stamp unit (TSU)
    · Support for 802.1AS timing and synchronization
    · Supports RMII Interface to the physical layer
    · Compatible with IEEE Standard 802.3
    · 10 and 100 Mbit/s Operation
    · Full-duplex and Half-duplex Operation
    · Statistics Counter Registers
    · Interrupt Generation to Signal Receive and Transmit Completion
    · DMA Master on Receive and Transmit Channels
    · Transmit and Receive FIFOs
    · Automatic Pad and CRC Generation on Transmitted Frames
    · Automatic Discard of Frames Received with Errors
    · Address Checking Logic Supports Up to Four Specific 48-bit Addresses
    · Supports Promiscuous Mode Where All Valid Received Frames are Copied to Memory
    · Hash Matching of Unicast and Multicast Destination Addresses
    · Physical Layer Management through MDIO Interface
    · Half-duplex Flow Control by Forcing Collisions on Incoming Frames
    · Full-duplex Flow Control with Recognition of Incoming Pause Frames
    · Support for 802.1Q VLAN Tagging with Recognition of Incoming VLAN and Priority Tagged Frames
    · Multiple Buffers per Receive and Transmit Frame
    · Wake-on-LAN Support
    · Jumbo Frames Up to 10240 bytes Supported
    · Compatible with MultiMedia Card Specification Version 4.3
    · Compatible with SD Memory Card Specification Version 2.0
    · Compatible with SDIO Specification Version 2.0
    · Compatible with CE-ATA Specification 1.1
    · Cards Clock Rate Up to Master Clock Divided by 2
    · Boot Operation Mode Support
    · High Speed Mode Support
    · Embedded Power Management to Slow Down Clock Rate When Not Used
    · Supports 1 Multiplexed Slot(s)
    · Each Slot for either a High Speed MultiMedia Card Bus (Up to 30 Cards) or an SD Memory Card
    · Support for Stream, Block and Multi-block Data Read and Write
    · Supports Connection to DMA Controller (DMAC)
    · Minimizes Processor Intervention for Large Buffer Transfers
    · Built in FIFO (from 16 to 256 bytes) with Large Memory Aperture Supporting Incremental Access
    · Support for CE-ATA Completion Signal Disable Command
    · Protection Against Unexpected Modification On -the-Fly of the Configuration Registers
    · Supports Communication with Serial External Devices
    · Master Mode can drive SPCK up to peripheral clock (bounded by maximum bus clock divided by 2)
    · Slave Mode operates on SPCK, asynchronously to Core and Bus Clock
    · Four Chip Selects with External Decoder Support Allow Communication with Up to 15 Peripherals
    · Serial Memories, such as DataFlash and 3-wire EEPROMs
    · Serial Peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors
    · External Coprocessors
    · Master or Slave Serial Peripheral Bus Interface
    · 8-bit to 16-bit Programmable Data Length Per Chip Select
    · Programmable Phase and Polarity Per Chip Select
    · Programmable Transfer Delay Between Consecutive Transfers and Delay before SPI Clock per Chip Select
    · Programmable Delay Between Chip Selects
    · Selectable Mode Fault Detection
    · Connection to DMA Channel Capabilities Optimizes Data Transfers
    · One channel for the Receiver, One Channel for the Transmitter
    · 3 TWIs
    · Compatible with Atmel Two-wire Interface Serial Memory and I2C Compatible Devices
    · One, Two or Three Bytes for Slave Address
    · Sequential Read-write Operations
    · Master, Multi-master and Slave Mode Operation
    · Bit Rate: Up to 400 Kbit/s
    · General Call Supported in Slave mode
    · SMBUS Quick Command Supported in Master Mode
    · Connection to DMA Controller (DMA) Channel Capabilities Optimizes Data Transfers
    · Provides Serial Synchronous Communication Links Used in Audio and Telecom Applications
    · Contains an Independent Receiver and Transmitter and a Common Clock Divider
    · Interfaced with the DMA Controller (DMAC) to Reduce Processor Overhead
    · Offers a Configurable Frame Sync and Data Length
    · Receiver and Transmitter Can be Programmed to Start Automatically or on Detection of Different Events on the
    · Frame Sync Signal
    · Receiver and Transmitter Include a Data Signal, a Clock Signal and a Frame Synchronization Signal
    · System Peripheral to Facilitate Debug of Atmel? ARM?-based Systems
    · Composed of Four Functions
    · Two-pin UART
    · Debug Communication Channel (DCC) Support
    · Chip ID Registers
    · ICE Access Prevention
    · Two-pin UART
    · Implemented Features are USART Compatible
    · Independent Receiver and Transmitter with a Common Programmable Baud Rate Generator
    · Even, Odd, Mark or Space Parity Generation
    · Parity, Framing and Overrun Error Detection
    · Automatic Echo, Local Loopback and Remote Loopback Channel Modes
    · Interrupt Generation
    · Support for Two DMA Channels with Connection to Receiver and Transmitter
    · Debug Communication Channel Support
    · Offers Visibility of COMMRX and COMM TX Signals from the ARM Processor
    · Interrupt Generation
    · Chip ID Registers
    · Identification of the Device Revision, Sizes of the Embedded Memories, Set of Peripherals
    · ICE Access Prevention
    · Enables Software to Prevent System Access Through the ARM Processor’s ICE
    · Prevention is Made by Asserting the NTRST Line of the ARM Processor’s ICE
    · Two-pin UART
    · Independent Receiver and Transmitter with a Common Programmable Baud Rate Generator
    · Even, Odd, Mark or Space Parity Generation
    · Parity, Framing and Overrun Error Detection
    · Automatic Echo, Local Loopback and Remote Loopback Channel Modes
    · Interrupt Generation
    · Support for Two DMA Channels with Connection to Receiver and Transmitter
    · Programmable Baud Rate Generator
    · 5- to 9-bit Full-duplex Synchronous or Asynchronous Serial Communications
    · 1, 1.5 or 2 Stop Bits in Asynchronous Mode or 1 or 2 Stop Bits in Synchronous Mode
    · Parity Generation and Error Detection
    · Framing Error Detection, Overrun Error Detection
    · MSB- or LSB-first
    · Optional Break Generation and Detection
    · By 8 or by 16 Over-sampling Receiver Frequency
    · Optional Hardware Handshaking RTS-CTS
    · Receiver Time-out and Transmitter Timeguard
    · Optional Multidrop Mode with Address Generation and Detection
    · RS485 with Driver Control Signal
    · ISO7816, T = 0 or T = 1 Protocols for Interfacing with Smart Cards
    · NACK Handling, Error Counter with Repetition and Iteration Limit
    · IrDA Modulation and Demodulation
    · Communication at up to 115.2 Kbps
    · SPI Mode
    · Master or Slave
    · Serial Clock Programmable Phase and Polarity
    · SPI Serial Clock (SCK) Frequency up to Internal Clock Frequency MCK/6
    · Test Modes
    · Remote Loopback, Local Loopback, Automatic Echo
    · Supports Connection of:
    · Two DMA Controller Channels (DMAC)
    · Offers Buffer Transfer without Processor Intervention
    · Fully Compliant with CAN 2.0 Part A and 2.0 Part B
    · Bit Rates up to 1 Mbit/s
    · 8 Object Oriented Mailboxes with the Following Properties:
    · CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message
    · Object Configurable in Receive (with Overwrite or Not) or Transmit Modes
    · Independent 29-bit Identifier and Mask Defined for Each Mailbox
    · 32-bit Access to Data Registers for Each Mailbox Data Object
    · Uses a 16-bit Timestamp on Receive and Transmit Messages
    · Hardware Concatenation of ID Masked Bitfields To Speed Up Family ID Processing
    · 16-bit Internal Timer for Timestamping and Network Synchronization
    · Programmable Reception Buffer Length up to 8 Mailbox Objects
    · Priority Management between Transmission Mailboxes
    · Autobaud and Listening Mode
    · Low Power Mode and Programmable Wake-up on Bus Activity or by the Application
    · Data, Remote, Error and Overload Frame Handling
    · Write Protected Registers
    · Channels
    · Common Clock Generator Providing Thirteen Different Clocks
    · A Modulo n Counter Providing Eleven Clocks
    · Two Independent Linear Dividers Working on Modulo n Counter Outputs
    · Independent Channels
    · Independent 16-bit Counter for Each Channel
    · Independent Complementary Outputs with 12-bit Dead-Time Generator (Also Called Dead-Band or Non-Overlapping Time) for Each Channel
    · Independent Enable Disable Command for Each Channel
    · Independent Clock Selection for Each Channel
    · Independent Period, Duty-Cycle and Dead-Time for Each Channel
    · Independent Double Buffering of Period, Duty-Cycle and Dead-Times for Each Channel
    · Independent Programmable Selection of The Output Waveform Polarity for Each Channel
    · Independent Programmable Center or Left Aligned Output Waveform for Each Channel
    · Independent Output Override for Each Channel
    · Independent Interrupt for Each Channel, at Each Period for Left-Aligned or Center-Aligned Configuration
    · 2 2-bit Gray Up/Down Channels for Stepper Motor Control
    · Synchronous Channel Mode
    · Synchronous Channels Share the Same Counter
    · Mode to Update the Synchronous Channels Registers after a Programmable Number of Periods
    · 2 Independent Events Lines Intended to Synchronize ADC Conversions
    · Programmable delay for Events Lines to delay ADC measurements
    · 8 Comparison Units Intended to Generate Interrupts, Pulses on Event Lines
    · 1 Programmable Fault/Break Inputs Providing an Asynchronous Protection of PWM Outputs
    · 4 User Driven through PIO inputs
    · PMC Driven when Crystal Oscillator Clock Fails
    · ADC Controller Driven through Configurable Comparison Function
    · Write Protected Registers
    · 12-bit Resolution
    · 1 MHz Conversion Rate
    · Wide Range Power Supply Operation
    · Selectable Single Ended or Differential Input Voltage
    · Programmable Gain For Maximum Full Scale Input Range 0 – VDD
    · Resistive 4-wire and 5-wire Touchscreen Controller
    · Position and Pressure Measurement for 4-wire screens
    · Position Measurement for 5-wire screens
    · Average of up to 8 measures for noise filtering
    · Programmable Pen Detection sensitivity
    · Integrated Multiplexer Offering Up to 12 Independent Analog Inputs
    · Individual Enable and Disable of Each Channel
    · Hardware or Software Trigger
    · External Trigger Pin
    · Timer Counter Outputs (Corresponding TIOA Trigger)
    · Internal Trigger Counter
    · Trigger on Pen Contact Detection
    · PWM Event Line
    · Drive of PWM Fault Input
    · DMA Support
    · Possibility of ADC Timings Configuration
    · Two Sleep Modes and Conversion Sequencer
    · Automatic Wakeup on Trigger and Back to Sleep Mode after Conversions of all Enabled Channels
    · Possibility of Customized Channel Sequence
    · Standby Mode for Fast Wakeup Time Response
    · Power Down Capability
    · Automatic Window Comparison of Converted Values
    · Write Protect RegistersCustomized Atmel Processor

Copyright © 2019 Maker I Am, Inc All Rights Reserved.